ARM Registers

• ARM exposes 37 registers in total.
• Registers sit in partially overlapping banks.
• Each processor mode has its own register bank.
• Banked registers make context switches for exceptions and privileged work fast.

General-purpose 32-bit registers

• Depending on mode, fifteen general-purpose registers (r0 through r14) are visible at once.
• R0–R10 are general use.
• R11–R15 have special roles.

r0

• Holds the return value.

r0–r3

• Pass function arguments. If there are more than four args, the rest go on the stack.

r11

• Holds the frame pointer for the current stack frame.

r13

• Stack pointer (SP) in ARM assembly.
• C and C++ compilers always use r13 as the stack pointer.
• PUSH and POP change its value.

r14

• After a BL in User mode, r14 is the link register (lr) and stores the return address for a subroutine call.
• If the return address is spilled to the stack, r14 can be used as a general register.

r15 — program counter (PC)

• Access the program counter as r15 (or pc).
• In ARM state it advances by one word (4 bytes) per instruction.
• In Thumb state it advances by 2 bytes.
• Branch instructions load the target into the program counter.
• You can also load the PC directly with a data-processing instruction.

MOV pc, lr

• To return from a subroutine, copy the link register into the program counter as above.
• While executing, r15 does not hold the address of the currently executing instruction.
• That address is usually pc-8 in ARM state and pc-4 in Thumb state.

Current Program Status Register (CPSR)

• Copy of the ALU status flags
• Current processor mode
• Interrupt disable flags
• CPSR ALU flags decide whether a conditional instruction runs.
• On Thumb-capable CPUs, CPSR also records ARM vs Thumb state.
• In ARM architecture v5TE, CPSR also holds the Q flag.

• Condition code flags
  • N = Negative result from ALU
  • Z = Zero result from ALU
  • C = ALU operation Carried out
  • V = ALU operation overflowed

Five SPSRs (Saved Program Status Registers)

• An SPSR saves CPSR when an exception is taken.
• Each exception mode has one accessible SPSR.
• User and System modes are not exception modes, so they have no SPSR.