CISC (Complex Instruction Set Computer)

CISC keeps a large, rich instruction set. Decoding takes longer, and variable-length ops make deep pipelines harder to design.

What "complex" means here

하나의 명령어가 할 수 있는 일의 양이 RISC 대비하여 많다는 것을 의미
명령어 마다 길이가 다르며 동작에 있어 사이클 수도 다르기 때문에 pipelining 설계가 어렵다.
1~100 byte 이상 되는 명령어들 도 있다.

One instruction can do more work than a typical RISC op. Length and cycle count vary per instruction, so pipelining is awkward. Some encodings stretch past 100 bytes.

RISC (Reduced Instruction Set Computer)

RISC shrinks the instruction inventory so the hardware stays simpler.

• Fixed-length instructions (classically 32-bit on ARM)
• A smaller set of core operations
• Pipelining becomes practical, which helped speed, silicon simplicity, and cost

Why ARM uses RISC

ARM descends from Berkeley RISC. The usual traits:

Load-Store 방식
Fixed-Length 32bit Instruction
3-address Instruction

ARM processor operation modes

Classic ARM defines seven operation modes. A mode is the processor's privilege and exception context. Each mode has its own stack pointer (SP), except User and System, which share a stack.

User Mode (US) — CPSR M[10000]

Normal application mode. It is the only non-privileged mode. Memory and I/O access are restricted so user mistakes stay contained. Entering SVC needs a software interrupt.

Fast Interrupt Mode (FIQ) — CPSR M[10001]

Fast interrupt handling. Of the two interrupt sources, FIQ is the high-priority path. It sits at the bottom of the exception vector table and owns extra banked registers so handlers can avoid saving as much state.

Supervisor Mode (SVC) — CPSR M[10011]

OS-protected mode reached via software interrupt. Kernel and device-driver system calls run here. Reset and SWI both enter SVC.

Abort Mode (ABT) — CPSR M[10111]

Entered on data abort or instruction prefetch abort — faults while fetching or accessing memory. Kernel panics often land here with a useful stack snapshot.

Interrupt Mode (IRQ) — CPSR M[10010]

General-purpose hardware interrupt mode. External IRQ lines switch the core into IRQ and run the handler.

System Mode (SYS) — CPSR M[11111]

Privileged OS mode that uses the same register bank as User. Same registers, different privilege.

Undefined Mode (UND) — CPSR M[11011]

Entered when the core hits an undefined instruction exception.

CPSR

The current mode lives in a 5-bit field (bits 0–4) of the Current Program Status Register. The remaining CPSR bits hold condition codes (N, Z, C, V) and other control state.

Mode changes

Interrupts, faults, and deliberate software paths change mode.

User and System share a stack; User still cannot touch privileged resources freely. SVC is the post-reset mode and manages system resources on its own stack. When user code needs OS services, it takes a system call into SVC.

ARM and Thumb state

From ARMv4T onward, Thumb adds a 16-bit instruction set that is a functional subset of 32-bit ARM. Running Thumb code means Thumb state; running ARM code means ARM state. You cannot execute Thumb encodings in ARM state or ARM encodings in Thumb state. Each set includes instructions that switch state. After reset, the core always starts in ARM state.